1. Field of the Invention
This invention relates to a direct spread type spread spectrum receiver and, more particularly, it relates to a spread spectrum receiver adapted to prevent the occurrence of phase errors in the transmitter side PN code and the receiver side PN code when a phase-locked loop is used for establishing and holding synchronism.
2. Description of the Prior Art
The spread spectrum communication system has been well known as a radio communications system. With the spread spectrum system, the transmitter side modulates the carrier wave by means of an information signal, such as an audio signal or a data signal, and the modulated information signal is multiplied by a spreading code such as an Maximum length sequence spreading code (Maximum length code) for spectral spread. The spectrally spread signal is then transmitted by way of an antenna. On the receiver side, on the other hand, the received spread spectrum signal is multiplied by the same spreading code for despreading and demodulated to reproduce the original information signal.
With the spread spectrum communication system, the spreading code prepared by the receiver and the spreading code contained in the signal being received have to be synchronized and the received spread spectrum signal has to be multiplied by the prepared spreading code. A spread spectrum receiver as shown in FIG. 1 has been proposed and used for maintaining the synchronism of the spreading code prepared by the receiver side and the spreading code contained in the signal being received. Referring to FIG. 1, the received spread spectrum signal is subjected to frequency conversion to a lower frequency in a frequency conversion circuit (1) to facilitate the processing operations in the downstream circuits and subsequently multiplied in a multiplier (2) by the spreading code generated using a spreading code generating circuit (3). The output signal of the multiplier (2) is then compared with the output signal of a VCXO (voltage controlled crystal oscillator) (5) for phase comparison in a phase comparator circuit (4). The output signal of the phase comparator circuit (4) that reflects the outcome of the phase comparison is smoothed by an LPF (6) and thereafter applied to the VCXO (5) as a control signal so that the oscillation frequency of the VCXO (5) is altered according to the control signal. The output signal of the VCXO (5) is applied to the phase comparator circuit (4) and, at the same time, frequency-divided by a frequency divider (7) before being applied to the spreading code generating circuit (3). Note that the multiplier (2), the phase comparator circuit (4), the VCXO (5) and the LPF (6) form a PLL (phase-locked loop), which operates to nullify the phase difference between the two input signals of the phase comparator circuit (4). Thus, the timing of generating a spreading code of the spreading code generating circuit (3) changes according to the change in the oscillation frequency of the VCXO (5) and the PLL operates to synchronize the phases of the two input signals from the phase comparator circuit (4) so that consequently the phase of the output signal of the multiplier (2) and that of the output signal of the VCXO (5) become synchronized.
After the PLL is locked, a spreading code that is synchronized with the spread spectrum signal is generated by the spreading code generating circuit (3) and the spread spectrum signal is multiplied by the spreading code in the multiplier (2) for despreading. The output signal of the multiplier (2) generated by despreading is applied to a demodulator circuit (9) via the BPF (8) to reproduce the information signal by demodulation.
Referring to FIG. 1, the PLL operates to synchronize the phases of the two input signals of the phase comparator circuit in order to nullify the phase difference between the output signal of the multiplier (2) and that of the VCXO (5). However, in reality, the phase of the spreading code prepared by the receiver side and that of the spreading code contained in the received spread spectrum signal do not accurately coincide with each other and precise despreading cannot be realized due to the delay in the operation of some of the elements constituting the circuit of FIG. 1.